1. Field of the Invention
Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a pre-metal dielectric layer using a chemical mechanical polishing process.
2. Description of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large-scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, trenches and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Multilevel interconnects are formed using sequential material deposition and material removal techniques on a substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarization or “polishing” is a process in which material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material, removing undesired surface topography, and surface defects, such as surface roughness, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent photolithography and other semiconductor manufacturing processes.
Chemical Mechanical Planarization, or Chemical Mechanical Polishing (CMP), is a common technique used to planarize substrates. CMP utilizes chemical compositions, such as slurries or other fluid medium, for selective removal of materials from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate, thereby pressing the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus affects polishing or rubbing movements between the surface of the substrate and the polishing pad while dispersing a polishing composition to affect chemical activities and/or mechanical activities and consequential removal of materials from the surface of the substrate.
Shallow trench isolation (STI) provides an efficient means of producing integrated circuits. In the STI process, CMP is used to planarize an oxide to expose a nitride stop.
One objective of CMP is to achieve global planarization by reducing global step height between areas of different density and/or size within each substrate as well as achieving uniform surface topography from substrate to substrate when performing a batch polishing process.
Therefore, there is a need for a polishing process which accurately and reliably removes a predictable amount of material while achieving global planarization within each substrate as well as achieving uniform surface topography from substrate to substrate.